Conventional vs. junctionless gate-stack DG-MOSFET based CMOS inverter

International Journal of Nano Dimension

مقاله 2، دوره 12، شماره 2، تیر 2021، صفحه 98-103   

نوع مقاله: Reasearch Paper

شناسه دیجیتال (DOI): 10.22034/ijnd.2021.677807

نویسندگان

Shubham Tayal^{* 1}؛ Pachimatla Samrat²؛ Vadula Keerthi²؛ Biswajit Jena³؛ Karthik Rajendra⁴

¹Department of Electronics & Communication Engineering, Sree Dattha Institute of Engineering and Science, Telangana, India.

²Department of ECE, Ashoka Institute of Engineering & Technology, Hyderabad, Telangana, India.

³Department of ECE, Koneru Lakshmaiah Education Foundation, Amaravati nehi Vaddeswaram, India.

⁴Department of Electronics and Communication Engineering, MLR Institute of Technology, Hyderabad, Telangana, India.

چکیده

In this article, the high-k gate dielectric effect on the operation of complementary metal oxide semiconductor (CMOS) inverter build using conventional (CL) double-gate (DG) metal oxide semiconductor field effect transistor (MOSFET) and junctionless (JL) double-gate (DG) MOSFET has been explored. It is found that the improvement in inverter performance is more pronounced in CL-DG-MOSFET based CMOS inverter in comparison to JL-DG-MOSFET based CMOS inverter when SiO₂ is replaced by the high-k dielectric at gate oxide. The improvement in low noise margin (ΔNM_L), high noise margin (ΔNM_H), gain (ΔA) & propagation delay (Δp < sub>d) is 3.19%, 1.64%, 5.2% & 0.9% respectively when SiO₂ is replaced by TiO₂ at gate oxide in case of CL-DG-MOSFET based CMOS inverter whereas it is 1.96%, 1.24%, 3.4% & 1.71% respectively in case of JL-DG-MOSFET based CMOS inverter. Consequently, the utilization of high-k dielectric as gate oxide is more advantageous in CL-DG-MOSFET devices for improved stability and gain of CMOS inverter.

کلیدواژه‌ها

CMOS Inverter؛ DG-MOSFET؛ Gate-Stack؛ High-k؛ Junctionless

مراجع

[1]     Mohapatra N. R., Desai M. P., Narendra S. G., Rao V. R., (2002), The effect of high-K gate dielectrics on deep sub-micrometer CMOS device and circuit performance. IEEE Trans. Electron Dev. 49: 826-831.

[2]     Zhang W., Fossum J. G., Mathew L., Du Y., (2005), Physical insights regarding design and performance of independent-gate FinFETs. IEEE Trans. Electron Dev. 52: 2198-2206.

[3]     Tayal S., Nandi A., (2017), Analog/RF performance analysis of channel engineered high-k gate-stack based junctionless trigate-FinFET. Superlatt. Microst. 112: 287-295.

[4]     Bozorgi Golafzani A., Sedigh Ziabari S., (2020), Representation of a nanoscale heterostructure dual material gate JL-FET with NDR characteristics. Int. J. Nano. Dimens. 11: 12-17.

[5]     Colinge J. P., Lee C.-W., Afzalian A., Akhavan N. D., Yan R., Ferain I., Razavi P., O’Neill B., Blake A., White M., Kelleher A.-M., McCarthy B., Murphy R., (2010), Nanowire transistors without junctions. Nat. Nanotechnol. 5: 225-229.

[6]     International Technology Roadmap for Semiconductor (ITRS) for Radio Frequency and Analog/Mixed-signal Technologies, (2013), www.itrs.net.

[7]     Tayal S., Nandi A., (2017), Analog/RF performance analysis of inner gate engineered junctionless Si nanotube. Superlatt. Microst. 111: 862-871.

[8]     Momose H. S., Ono M., Yoshitomi T., Ohguro T., Nakamura S.  I., Saito M., Iwai H., (1996), 1.5 nm direct-tunneling gate oxide Si MOSFET’s. IEEE Trans. Elect. Dev. 43: 1233-1242.

[9]     Jena B., Dash S., Mishra G. P., (2018), Improved switching speed of a CMOS inverter using work-function modulation engineering. IEEE Trans. Elect. Dev. 65: 2422-2429.

[10]  Tayal S., Nandi A., (2017), Comparative analysis of high-k gate stack based conventional & junctionless FinFET, in Proc. of 14^th IEEE India Council International Conf. (INDICON),  1-4.

[11]  Tayal Sh., Samrat P., Keerthi V., Vandana B., Gupta Sh., (2020), Channel thickness dependency of high-k gate dielectric based double-gate CMOS inverter. Int. J. Nano. Dimens. 11: 215-221.

[12]  Mohapatra S. K., Pradhan K. P., Sahu P. K., (2014), Influence of high-K dielectric on nanoscale DG-MOSFET. IJAST. 65: 19-26.

[13]  Chowdhury M. H., Mannan M. A., Mahmood S. A., (2010), High-K dielectrics for submicron MOSFETs. IJETSE. 2: 8-10.

[14]  Prerna M., (2013), Future MOSFET devices using high-k (TiO₂) dielectric. IJRASET. 1: 23-28.

[15]  Tayal S., Nandi A., (2018), Optimization of gate stack in junctionless Si-nanotube FET for analog/RF applications. Mater. Sci. Semicond. Proc. 80: 63-67.

[16]  Pradhan K. P., Mohapatra S. K., Sahu P. K., Behera D. K., (2014), Impact of high-K dielectric on analog and RF performance of nanoscale DGMOSFET. Microelectron. J.  45: 144-151.

[17]  Sentarus Device User Guide. Available: http://www.synopsys.com.

[18]  Tayal S., Nandi A., (2018), Effect of high-K gate dielectric in-conjunction with channel parameters on the performance of FinFET based 6T SRAM. J. Nanoelectron. Optoelec. 13: 768-774.

[19]  Tayal S., Nandi A., (2018), Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM. Micro Nano Lett. 13: 965-968.

[20]  Granzner R., Polyakov V. M., Schwierz F., Kittler M., Doll T., (2003), On the suitability of DD and HD models for the simulation of nanometer double-gate MOSFETs. Phys. E. 19: 33-38.

[21]  Tayal S., Nandi A., (2017), Study of 6T SRAM cell using high-k gate dielectric based junctionless silicon nanotube FET. Superlatt. Microst. 112: 143-150.

[22]  Dixit A., Kottantharayil A., Collaert N., Goodwin M., Jurczak M., Meyer K. D., (2005), Analysis of the parasitic S/D resistance in multiple-gate FETs. IEEE Trans. Elect. Dev. 52: 1132-1140.

[23]  Nuttinick S., Parvais B., Curatola G., Mercha A., (2007), Double-gate FinFETs as a CMOS technology downscaling option: An RF perspective. IEEE Trans. Elect. Dev. 54: 279-283.

[24]  Tayal S., Nandi A., (2018), Performance analysis of junctionless DG-MOSFET based 6T SRAM with gate-stack configuration. Micro Nano Lett. 13: 838-841. 

[25]  Tayal S., Nandi A., (2017), Effect of FIBL in-conjunction with channel parameters on analog and RF FOM of FinFET. Superlatt. Microst. 105: 152-162.

[26]  Tayal S., Nandi A., (2018), Interfacial layer dependence of high-k gate stack based conventional trigate FinFET concerning analog/RF performance, in Proc. of 4^th International Conf. on Devices, Circuits and Systems (ICDCS). 305-308.

[27]  Rabey J. M., Chandrakasan A. P., Nikolic B., (2003), Digital Integrated Circuits: A Design Perspective, Pearson Education.

[28]  Tewari S., Biswas A., Malik A., (2015), Investigation of high-performance CMOS with p-Ge and n-InGaAs MOSFETs for logic applications. IEEE Trans. Nano. 14: 275-281.