تعداد نشریات | 418 |
تعداد شمارهها | 9,997 |
تعداد مقالات | 83,560 |
تعداد مشاهده مقاله | 77,801,236 |
تعداد دریافت فایل اصل مقاله | 54,843,893 |
Soft Error Rate Estimation of Logic Circuits Using Recurrent Neural Networks | ||
Journal of Computer & Robotics | ||
مقاله 5، دوره 12، شماره 2، اسفند 2019، صفحه 49-56 اصل مقاله (1.03 M) | ||
نوع مقاله: Original Research (Full Papers) | ||
نویسندگان | ||
Rasoul Farjaminezhad1؛ saeed safari* 2؛ Amir Masoud Eftekhari Moghadam3 | ||
1Computer architecture, Neural Networks | ||
2Computer Architecture Digital Systems | ||
3Image Retrieval, Pattern Recognition, Image Mining, Multimedia Databases | ||
چکیده | ||
Nano-scale technology has brought more susceptibility to soft errors for the generation of complicated and state of the art devices. Soft errors are the impacts of radiation of the particles like a neutron, alpha, and ions on the surface of the circuits. To tackle the system malfunctions and provide a reliable device, studying the transient fault effects on the logic circuits can be a more significant issue. This paper presents a new approach based on Recurrent Neural Networks (RNNs) to estimate ICs' Soft Errors Rate (SER). As RNN can be deployed for signal processing and time series, we applied it to investigate transient fault effects while propagating through the combinational and sequential parts of a test chip and compute its SER by simulating and analyzing the circuit outputs. In this paper, the results of utilizing the proposed RNN model to estimate the SER of the ISCAS-85 benchmark circuits have been provided. | ||
کلیدواژهها | ||
recurrent neural networks؛ circuit modeling؛ transient fault؛ soft error rate | ||
مراجع | ||
[1] G. I. Paliaroutis, P. Tsoumanis, N. Evmorfopoulos, G.Dimitriou and G. I. Stamoulis, "A Placement-Aware Soft Error Rate Estimation of Combinational Circuits for Multiple Transient Faults in CMOS Technology," in 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Chicago, IL,USA, 8-10 Oct. 2018. [2] A. Balakrishnan, T. Lange, M. Glorieux, D. Alexandrescu and M. Jenihhin, "Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects," in 2020 9th Mediterranean Conference on Embedded Computing (MECO), Budva, Montenegro, Montenegro, 8-11 June 2020. [3] S. Mukherjee, C. Weaver, J. Emer, S. Reinhardt, and T.Austin, "A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor," in Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003.MICRO-36, San Diego, CA, USA, USA, 5-5 Dec. 2003. [4] Y.-H. Kuo, H.-K. Peng and C. H.-P. Wen, "Accurate statistical soft error rate (SSER) analysis using a quasi-Monte Carlo framework with quality cell models," in 2010 11th International Symposium on Quality Electronic Design (ISQED), San Jose, CA, USA, 22-24 March 2010. [5] Mohammad Eslamia, Behnam Ghavamia, Mohsen Rajib and AliMahani, "A survey on fault injection methods of digital integrated circuits," ScienceDirect, Integration, the VLSI Journal, vol. 71, pp. 154-163, 11 November 2019. [6] M. Anglada, R. Canal, J. L. Aragón and A. González,"MASkIt: Soft error rate estimation for combinational circuits," in 2016 IEEE 34th International Conference on Computer Design (ICCD), Scottsdale, AZ, USA, 2-5 Oct. 2016. [7] Y. Dhillon, A. Diril and A. Chatterjee, "Soft-error tolerance analysis and optimization of nanometer circuits," in Design,Automation, and Test in Europe, Munich, Germany,Germany, 7-11 March 2005. [8] J. F. Ziegler, H. W. Curtis, H. P. Muhlfeld, C. J. Montrose, B.Chin, M. Nicewicz, C. A. Russell, W. Y. Wang, L. B. Freeman, P. Hosier, L. E. LaFave, J. L. Walsh, J. M. Orro, G.J. Unger, J. M. Ross, T. J. O'Gorman, B. Messina, T. D. Sullivan, A. J. Sykes, H. Yorke, and T. A. E, "IBM experiments in soft fail in computer electronics (1978–1994)," IBM Journal of Research and Development, vol. 40, no. 1, pp.3 - 18, Jan. 1996. [9] M. Zhang and N. Shanbhag, "Soft-Error-Rate-Analysis (SERA) Methodology," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no.10, pp. 2140 - 2155, Oct. 2006. [10] P. Dodd and L. Massengill, "Basic mechanisms and modeling of single-event upset in digital microelectronics," IEEE Transactions on Nuclear Science, vol. 50, no. 3, pp. 583 - 602,June 2003. [11] Z. Naghibi, S. A. Sadrossadat, and S. Safari, "Time-domain modeling of non-linear circuits using deep recurrent neural network technique," AEU - International Journal of Electronics and Communications, vol. 100, pp. 66-74, February 2019. [12] G. Srinivasan, P. Murley and H. Tang, "Accurate, predictive modeling of soft error rate due to cosmic rays and chip alpha radiation," in Proceedings of 1994 IEEE International Reliability Physics Symposium, San Jose, CA, USA, USA,11-14 April 1994. [13] D. P. Kingma and J. L. Ba, "ADAM: A METHOD FOR STOCHASTIC OPTIMIZATION," in 3rd International Conference for Learning Representations (ICLR), San Diego,2015. [14] R. Rajaraman, J. Kim, N. Vijaykrishnan, Y. Xie and M.Irwin, "SEAT-LA: a soft | ||
آمار تعداد مشاهده مقاله: 264 تعداد دریافت فایل اصل مقاله: 172 |