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Design, simulation and analysis of high-K gate dielectric FinField effect transistor | ||
International Journal of Nano Dimension | ||
مقاله 10، دوره 12، شماره 3، مهر 2021، صفحه 305-309 اصل مقاله (923.86 K) | ||
نوع مقاله: Short Communication | ||
شناسه دیجیتال (DOI): 10.22034/ijnd.2021.681554 | ||
نویسندگان | ||
Marupaka Aditya1؛ Karumuri Srinivasa Rao* 1؛ Kondavitee Girija Sravani1، 2؛ Koushik Guha2 | ||
1MEMS Research Center, Department of Electronics and Communication Engineering, KoneruLakshmaiah Education Foundation (Deemed to be University), Green Fields, Vaddeswaram, Andhra Pradesh, India. | ||
2National MEMS Design Center, Department of Electronics and Communication Engineering, National Institute of Technology, Silchar, Assam, India. | ||
چکیده | ||
The devices with additional gates like Fin Field effect transistor (FinFET) provide higher control on subthreshold parameters and are favorable for Ultra large-scale integration. Also, these structures provide high control on current through the channel and with minimum leakage. In this paper we designed a FinFET with high-K gate dielectric material i.e Hafnium oxide as gate oxide. A comparison of similar sized transistor with Air and Silicon dioxide as gate material is performed. The comparison is mainly in terms of performance parameters like transconductance, subthreshold slope, and drain current characteristics. There is an increase in ON current on using a high-K dielectric material and subsequently an improvement in other parameters like subthreshold slope, transconductance and intrinsic gain. | ||
کلیدواژهها | ||
FinFET؛ Hafnium Oxide؛ High-K Dielectric؛ Subthreshold Slope؛ Transconductance | ||
مراجع | ||
[1] Roy K., Mukhopadhyay S., Mahmoodi-Meimand H., (2003), Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE. 91: 305–327.
[2] Frank D. J., Dennard R. H., Nowak E., Solomon P. M., Taur Y., Wong H. S. P., (2001), Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE. 89: 259–288.
[3] Solomon P. M., Guarini K. W., Zhang Y., (2003), Two gates are better than one. IEEE Circuits Devices Mag. 19: 48–62.
[4] Suzuki K., Tanaka T., Tosaka Y., Horie H., Arimoto Y., (1993), Scaling theory for double-gate SOI MOSFET’s. IEEE Tran. Elec. Dev. 40: 2326–2329.
[5] Bhattacharya D., Jha N. K., (2014), FinFETs: From devices to architectures. Adv. Electronics. 2: 1-21.
[6] Hisamoto D., Lee W.-C., Kedzierski J., (2000), FinFET—as selfaligned double-gate MOSFET scalable to 20 nm. IEEE Tran. Elec. Dev. 47: 2320–2325.
[7] Saha R., Bhowmick B., Baishya S., (2018), 3D analytical modeling of surface potential, threshold voltage, and subthreshold swing in dual- material-gate (DMG) SOI FinFETs. J. Comp. Elect. 12: 153-162.
[8] Saha R., Bhowmick B., Baishya S., (2017), Effects of temperature on electrical pa- rameters in GaAs SOI FinFET and application as digital inverter. Dev. Integ. Circuit (DevIC). 4: 462-466.
[9] Mendiratta N., Tripathi S., (2020), A review on performance com- parison of advanced MOSFET structures below 45 nm technology node. J. Semiconduct. 6: 1-10.
[10] Colinge J.-P., (2008), FinFETs and other multi-gate transistors. Springer, New York, NY, USA.
[11] Datta A., Goel A., Cakici R. T., Mahmoodi H., Lekshmanan D., Roy K., (2007), Modeling and circuit synthesis for independently controlled double gate FinFET devices. IEEE Tran. Computer-Aided Des. Integ. Circ. Sys. 26: 1957–1966.
[12] Tawfik S. A., Kursun V., (2008), Low-power and compact sequential circuits with independent-gate FinFETs. IEEE Tran. Electron Dev. 55: 60–70.
[13] Swahn B., Hassoun S., (2006), Gate sizing: FinFETs vs 32 nm bulk MOSFETs. Proc. 43rd IEEE Des. Automation Conf. 528–531.
[14] Bhoj A. N., Simsir M. O., Jha N. K., (2012), Fault models for logic circuits in the multigate era. IEEE Tran. Nanotech. 11: 182–193.
[15] Palanichamy V., Kulkarni N., Thankamony Sarasam A., (2019), Improved drain current characteristics of tunnel field effect transistor with heterodielectric stacked structure. Int. J. Nano Dimens. 10: 368-374.
[16] Tayal S., Samrat P., Keerthi V., Vandana B., Gupta S., (2020), Channel thickness dependency of high-k gate dielectric based double-gate CMOS inverter. Int. J. Nano Dimens. 11: 215-221.
[17] Khorramrouz F., Sedigh Ziabari S., Heydari A., (2018), Analysis and study of geometrical variability on the performance of junctionless tunneling field effect transistors: Advantage or deficiency? Int. J. Nano Dimens. 9: 260-272.
[18] Hasan M., Kumer A., Chakma U., (2020), Theoretical investigation of doping effect of Fe for SnWO4 in electronic structure and optical properties: DFT based first principle study. Adv. J. Chem. Sec. A. 3: 639-644.
[19] Chakma U., Kumer A., Chakma K., Islam M., Howlader D., (2020), Electronics structure and optical properties of Ag2BiO3, (Ag2) 0.88 Fe 0.12BiO3: A first principle approach. Adv. J. Chem. Sec. A. 3: 542-550.
[20] Das S., Ekka D., Roy M., (2020), Conductance and FTIR spectroscopic study of triple-ion formation of Tetrabutylphosphonium Methanesulfonate in Methylamine solution. Chem. Methodol. 4: 55-67. | ||
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