طراحی یک مقایسه کننده کم توان سرعت بالا با سطح اشغالی کم در فناوری فین فت ۶۵ نانومتری

مهندسی مخابرات جنوب

دوره 11، شماره 44، تیر 1401، صفحه 9-18   

نوع مقاله: مقاله پژوهشی

شناسه دیجیتال (DOI): 10.30495/jce.2022.691133

نویسندگان

نوید سبزواری¹؛ محمدرضا یوسفی²؛ سیدمحمدعلی زنجانی^{* 3}

¹گروه مهندسی برق، دانشگاه آزاد اسلامی واحد نجف آباد، نجف آباد، ایران

²مرکز تحقیقات ریز شبکه های هوشمند، دانشگاه آزاد اسلامی واحد نجف آباد، نجف آباد، ایران

³مرکز تحقیقات ریزشبکه های هوشمند، دانشگاه آزاد اسلامی واحد نجف آباد، نجف آباد، ایران

چکیده

در این مقاله، یک مدار مقایسه ­کننده جدید کم ­توان و پرسرعت به­کمک ترانزیستور اثر میدان باله ­ای (Finfet) در فناوری 65 نانومتری طراحی شده است. علاوه بر این، با استفاده صحیح از قابلیت ­های فناوری Finfet، تعداد ترانزیستورها کاهش یافته و درنتیجه، سطح کمتری اشغال می ­شود. جایگزینی ترانزیستورهای MOSFET با Finfet باعث کاهش تأخیر و مصرف توان مدار شده، عملکرد کلی مدار بهبود می­ یابد. اولین نوآوری در طرح پیشنهادی این است که برای کاهش اندازه و مصرف توان، دو ترانزیستور حذف شده ­اند و گیتهای پشتی دو ترانزیستور به­صورت متقاطع قرار گرفته ­اند. نوآوری دوم، اتصال گیتهای پشتی به نقاط مناسبی از مدار است که سرعت مقایسه را افزایش می­دهد. در این مطالعه، تغذیه 0.8 ولت به مدار اعمال می­شود تا نشان دهد که مدار پیشنهادی با Finfet باعث کاهش تأخیر به 272 پیکوثانیه و مصرف توان به  6.7میکرووات می­شود.

کلیدواژه‌ها

مقایسه‌کننده؛ ترانزیستور اثر میدان باله‌ای؛ سرعت بالا؛ سطح کم اشغالی؛ کم توان

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