Hardware Implementation of High-Speed Low-Power Viterbi Decoder for Deep-Space Communication

Majlesi Journal of Telecommunication Devices

مقاله 6، دوره 5، شماره 4، فروردین 2016   

نوع مقاله: Articles

نویسندگان

Ali Ghasemi khah^* ؛ Yosef Seifi Kavian

Shahid Chamran university of Ahvaz

چکیده

In communication systems, ensuring correct information reception is very important, Error Correction Coding methods have been developed in order to achieve this goal. Convolutional Code is used in Wireless, Satellite, mobile phones and Deep-Space communications, it is one of the most powerful Error Correction code, and the Viterbi algorithm is robust way to decode it. Power conception and speed are two important feature of Viterbi decoders, in many communications the power consumption is most important. In this paper, by removing extra decoding cycles, the SMU registers are reduced by 20%, the power consumption reduced by 14.5% and the speed increased 6 times without error correction performance loss. The proposed design is described by VHDL and it is implemented on Xilinx Spartan3, Xc3s400 FPGA chip.

کلیدواژه‌ها

Convolutional code؛ en؛ Viterbi Decoder؛ FPGA؛ Deep-Space Communication

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