Design of a Digital Sigma Delta Modulator with Separate Pipeline Lines for Fractional Frequency Synthesizers

Majlesi Journal of Telecommunication Devices

مقاله 3، دوره 10، شماره 4، اسفند 2021، صفحه 159-163   

نوع مقاله: Articles

نویسندگان

Leila Jahan panah¹؛ Seyed Ali Sadatnoori^{* 2}؛ Iman Chaharmahali³

¹Department of Electrical Engineering, Mahshahr Branch, Islamic Azad University, Mahshahr, Iran

²Department of electrical Engineering, Shoushtar branch, Islamic Azad University, Shoushtar, Iran

³Department of Electrical Engineering, Andimeshk Branch, Islamic Azad University, Andimeshk, Iran

چکیده

Digital Sigma Delta Modulator architecture is widely used in fractional frequency synthesizers. A frequency synthesizer is a major component of wireless communication systems. The output of the frequency synthesizer system is locked based on the phase lock loop at a specific reference frequency. In this case, the output frequency is the same as the oscillator frequency of the VCO. The main advantage of digital sigma delta modulator with multi-layer structure is its ability to be implemented as a pipeline. This method will reduce the delay and increase the sampling frequency. In this paper, a digital sigma delta modulator of separate lines is designed by pipeline method and its power spectral density is plotted. This method increases the speed of the modulator and reduces the hardware consumption.

کلیدواژه‌ها

Digital Sigma Delta Modulator؛ Pipeline Method؛ Hardware Consumption؛ Speed

مراجع

[1] S. A. Sadatnoori, E. Farshidi and S. Sadughi, “A novel structure of dithered nested digital delta sigma modulator with low-complexity low-spur for fractional frequency synthesizers, ” COMPEL - The international journal for computation and mathematics in electrical and electronic,, vol. 35, No. 1, pp. 157-171, 2016.

[2] S. A. Sadatnoori, E. Farshidi and S. Sadughi, “A Novel Architecture of Pseudorandom Dithered MASH Digital Delta-Sigma Modulator with Lower Spur, ” Journal of Circuits, Systems and Computers, Vol: 25, No: 7, pp.1650072-1-18, 2016.

[3] M. P. Kennedy, H. Mo and B. Fitzgibbon, “Spurious tones in digital delta-sigma modulators resulting from pseudorandom dither”, journal of the Franklin Institute, pp. 1-20 , 2015.

[4] M. P. Kennedy, B. Fitzgibbon and K. Dobmeier, “Spurious Tones in Digital Delta Sigma Modulators with Pseudorandom Dither”, 978-1-4673-5762-IEEE, pp. 2747-2750, 2013.

[5] Z. Ye and M. P. Kennedy, “Hardware reduction in digital delta-sigma modulators via error masking—Part I: MASH DDSM”, IEEE Trans. Circuits Syst. I, Reg. Papers,Vol:56, No.4 ,pp. 714–726, 2009.

[6] Z. Ye and M. P. Kennedy, ““Hardware reduction in digital delta-sigma modulators via error masking—Part II: SQ-DDSM”,IEEE Trans. CircuitsSyst. II, Exp. Briefs, Vol: 56, No. 2, pp. 112–116, 2009.

[7] Y. Liao, X. Fan and Z. Hua. “Influence of LFSR Dither on the Periods of a MASH Digital Delta – Sigma Modulator”, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol: 66, No.1, pp. 66-70, 2019.

[8] L, Le, and G. Chen, “Designing and Optimizing of Sigma-Delta Modulator Using PSO Algorithm”, IEEE International Conference of Safety Produce Informatization (IICSPI), China, 2019.

[9] L. Toledo and L. Vazquez, “Continuous time full-feedforward MASH 2-2 architecture for Sigma-Delta Modulator”, 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2018.

[10] V. Mazzaro and M.P, Kennedy, “Mitigation of “Horn Spurs” in a MASH-Based Fractional-N CP-PLL”; IEEE Transactions on Circuits and Systems II: Express Briefs, Vol:67, No. 5,pp. 821-825, 2020.

[11] D. Mai and M.P, Kennedy, “Analysis of Wandering Spur Patterns in a Fractional- N Frequency Synthesizer With a MASH-Based Divider Controller”; IEEE Transactions on Circuits and Systems I: Regular Papers,Vol: 67, No. 3,pp. 729-742, 2020.