Hardware Implementation of 128-Bit AES Image Encryption with Low Power Techniques on FPGA to VHDL

Majlesi Journal of Electrical Engineering

مقاله 3، دوره 6، شماره 4، بهمن 2012   

نوع مقاله: Review Article

نویسندگان

Ali Farmani^* ؛ Hossein Balazadeh Bahar

University of Tabriz/Department Electrical and Computer Engineering, Tabriz

چکیده

This paper describes the implementation of a low power and high-speed encryption algorithm with high throughput for encrypting the image. Therefore, we select  a highly secured symmetric key encryption algorithm AES(Advanced Encryption Standard), in order to decrease the power using retiming and glitch and operand isolation techniques in four stages, control unit based on logic gates, optimal design of multiplier blocks in mixcolumn phase and simultaneous production  keys and rounds. Such procedure makes AES suitable for fast image encryption. Implementation of a 128-bit AES on FPGA of Altera Company has been done, and the results are as follows:  throughput, 6.5 Gbps in 441.5 MHz and 130mw power consumption. The time of encrypting in tested image with 32*32 sizes is 1.25ms.

کلیدواژه‌ها

prof.koze kanani؛ en؛ University of Tabriz؛ dean of department of electrical and computer engineering

مراجع

[1]N. Sloss, D. Symes, and C. Wright, ARM System Developer’s Guide, Designing and Optimizing System Software, Morgan Kaufmann, 2004.

[2]B. Gladman, A specification for Rijndael, the AES Algorithm. Available at http://fp.gladman.plus.com, May 2002.

[3]XYSSL Crypto Library, GNU Lesser General Public License, 2003.

[4]M. Zeghid, M. Machhout, L. Khriji, A. Baganne, and R. Tourki, A Modified AES Based Algorithm for Image Encryption,international journal of computer science engineering IEEE 2007.

[5]Kuo-huang chang,yi-cheng,chung-cheng,’’ Embedded a Low Area 32-bit AES for Image Encryption/Decryption Application ‘’2009 IEEE.

[6]Shuuen-shyang wang and wan-sheng ni,anefficient fpga implementation of advanced encryption standard algorithm,IEEE2004.

[7]Alireza hodjat,david d.hwang,bocheng lai,Ingrid verbauwhede,a 3.84 gbits/s AES crypto corprocessor with modes of operation in a0.18um cmos technology,IEEE 2005.

[8]XinmiaoZhang, Student Member IEEE and Keshab K.Parhi, Fellow,IEEE,High-Speed VLSI Architectures for the AES Algorithm IEEE TRANSACTION SONVERY LARGE SCALE INTEGRATION(VLSI) SYSTEMS,VOL.12,NO.9,SEPTEMBER 2004 .

[9]Chi-jeng Chang, Chi-Wu Husang,Hung-Yun Tai,Mao-Yuan Lin and Teng-KueiHu,8-bitAES FPGA Implementation ussing Block RAM,The 33 Annual Conference of the IEEE Industrial Electronics Society(IECON),Nov.5-8,2007 , Taipei , Taiwan.

[10]carl dreyer,A pipelined Implementation of AES for Altera FPGA platforms 2004.

[11]Chih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, and Cheng-Wen Wu, National Tsing Hua University” A High-Throughput Low-Cost AES Processor” IEEE Communications Magazine • December 2003.

[12]Namin Yu, Howard M. Heys ,Investigation of Compact Hardware Implementation of the Advanced Encryption Standard,2005 IEEE CCECE/CCGEI, Saskatoon, May 2005.

[13]Yi-Cheng Chen,Chung-Cheng Hsieh , Chi-WuHuang and Chi-Jeng Chang Kuo-Huang Chang,Embedded a Low Area 32-bit AES for Image Encryption/Decryption Application ,IEEE2009.

[14]AlirezaHodjat,StudentMember,IEEE,and Ingrid Verbauwhede, SeniorMember,IEEE, Area-ThroughputTrade-OfF for Fully Pipelined 30to70Gbits/s AES Processors, IEEE TRANS ACTIONSON COMPUTERS , VOL.55,NO.4,APRIL2006.

[15]Chi-Jeng Chang, Chi-Wu Huang, Kuo-Huang Chang, Yi-Cheng Chen and Chung-Cheng Hsieh, High Throughput 32-bit AES Implementation in FPGA,IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, December 2008 , MACAO , pp.1806-1809.(EI).

[16]Jyothi Yenuguvanilanka , Omar Elkeelany Performance Evaluation of Hardware Models of Advanced Encryption Standard (AES) Algorithm, 978-1-4244-1884-8/08/$25.00 2008 IEEE.

[17]Dazhong Wang , Xiaoni Li , Improved Method to Increase AES system Speed ,The Ninth International Conference on Electronic Measurement & Instruments ,ICEMI’2009.

[18]F.BurnsJ.MurphyA.KoelmansA.Yakovlev, EfficienT advanced encryption standard Implementation using lookup and normal basis, Published in IET Computers & Digital Techniques, IET Comput .Digit.Tech., 2009, Vol. 3, Iss. 3, pp. 270–280.

[19]L.Thulasimani, M.Madheswaran” A SINGLE CHIP DESIGN AND IMPLEMENTATION OF AES 128/192/256 ENCRYPTION ALGORITHMS” International Journal of Engineering Science and Technology Vol. 2(5), 2010, 1052-1059.

[20]XinmiaoZhang, Student Member, IEEE , and Keshab K.Parhi , Fellow, IEEE” High-Speed VLSI Architectures for the AES Algorithm” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS , VOL.12,NO.9 , SEPTEMBER 2004.

[21]Dessalegn Atnafu,”optimizing AES Implementation for high-speed embedded Application”,feb 2008,addis ababa.

[22]A.P. Chandrakasan, S.S. and Brodersen, R., 1992. Low-power CMOS Digital design, IEEE Journal of Solid-State Circuits, Apr., 27(4), pp. 473-484.

[23] McIvor,C., McLoone, M., and McCanny, J.V., 2004. Modified Montgomery modular multiplication and RSA exponentiation techniques, Proceedings of Computers and Digital Techniques, 151, pp. 402-408.

[24]Walter, C.D., 1999. Montgomery Exponentiation Needs No Final Subtraction, Electronic Letters, 35, pp. 1831-1832.

[25]Kaps, J.P., 2006. Cryptography for Ultra-Low Power Devices, Ph.D. thesis, Worcester Polytechnic Institue.

[26]Ghosh, A., Devadas, S., Keutzer, K. and White, J., 1992. Estimation of average switching activity in combinational and sequential circuits, DAC '92: Proceedings of the 29th ACM/IEEE conference on Design automation, pp. 253-259.

[27]Doğan, A.Y.,2008. AES Algoritmasının FPGA Üzerinde Düük Güçlü Tasarımı, M.Sc. Thesis, Istanbul Technical University, Istanbul.