A Novel Silicon on Diamond Structure to Improve Drain Induced Barrier Lowering

Majlesi Journal of Electrical Engineering

مقاله 9، دوره 7، شماره 1، خرداد 2013   

نوع مقاله: Review Article

نویسندگان

Arash Daghighi^{* 1}؛ Jafar Hoseini-Teshnizi²؛ GholamReza Amini³

¹Department of Electrical Engineering, Faculty of Engineering, Shahrekord University, Iran

²Department of Electrical Engineering, IAU NajafAbad Branch

³Faculty of Engineering, Shahrekord University

چکیده

A silicon on diamond structure to improve DIBL is presented. The electrical field penetration through the buried insulator of diamond degrades the DIBL. In the new structure, a second, double insulating material, e.g. SiO2 is added on top of the buried insulator and partially covers the diamond. The second insulating material has lower electrical permittivity. Therefore the fringing field capacitance is smaller. Simulation results of 22 nm silicon-on-diamond transistor shows 18% improvement in DIBL comparing with conventional SOD structure. Lattice temperature increase of 5% is observed in the new structure compared with the conventional SOD.

کلیدواژه‌ها

Drain Induced Barrier Lowering؛ en؛ Ultra Thin Body؛ Silicon on Diamond؛ MOSFET؛ Hydrodynamic Model

مراجع

[1] J. P. Mazellier, O. Faynot, S. Cristoloveanu, S.Deleonibus and P. Bergonzo, “Integration of diamond in fully-depleted silicon-on-insulator technology as buriedinsulator: A theoretical analysis,” Diamond & Related Material. Vol. 17, pp. 1248-1251, 2008.

[2] T. Skotnicki, “Materials and device structures for sub-32 nm CMOS nodes,” Microelectronic Engineering, Vol. 84, pp. 1845–1852, 2007.

[3] B. Svilicˇic´, V. Jovanovic´ and T. Suligoj, “Analytical models of front - and back-gate potential distribution and threshold voltage for recessed source/drain UTB SOI MOSFETs,” Solid-State Electronics. Vol. 53, pp. 540–547, 2009.

[4] Z. Zhang, S. Zhang, and M. Chan, “Self-Align Recessed Source Drain UltrathinBody SOI MOSFET,” IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 11, pp 740-742 NOVEMBER 2004.

[5] C. Z. Gu, Y. Sun, J. K. Jia, Z. S. Jin, “S OD wafer technology,” Microelectronic Engineering 66, pp 510–516, 2003.

[6] S. D. Wolter, G. N. Yushin, J. T. Prater, Z. Sitar, “Processing routes for direct bonding of silicon to epitaxially textured diamond,” Diamond and Related Materials 12 , pp 257–261, 2003.

[7] G. N. Yushin , A. Aleksov , S. D. Wolter , F.Okuzumi, J. T. Prater , Z. Sitar, “Wafer bonding of highly oriented diamond to silicon,” Diamond & Related Materials 13 , pp 1816– 1821, 2004.

[8] A. Aleksov , J. M. Gobien , X. Li, J. T. Prater, Z. Sitar, “Silicon-on-Diamond-An engineered substrate for electronic applications,” Diamond & Related Materials 15 pp 248 – 253 2006.

[9] DESSIS Manual, ISE integrated systems, 2004.

[10] S. Shao , S. Chung and J. S. Lee “A New Approach to Determine the Drain-and-Source Series Resistance of LDD MOSFET’s,” IEEE Trans. on Elec. Dev., Vol. 40, No. 9, pp 1709 – 1711, Sep. 1993.