بررسی رفتار نشست ولتاژ کنترل در مدارهای حلقه قفل فاز با در نظر گرفتن اثرات غیر ایده آل و حساسیت به تغییرات المانهای مدار

مهندسی مخابرات جنوب

دوره 12، شماره 48، تیر 1402، صفحه 13-28   

نوع مقاله: مقاله مروری

شناسه دیجیتال (DOI): 10.30495/jce.2023.1957910.1158

نویسندگان

ریحانه نظرآقایی¹؛ عبدالرسول قاسمی^{* 2}؛ نجمه چراغی شیرازی²

¹گروه برق، واحد بوشهر، دانشگاه آزاد اسلامی، بوشهر، ایران

²استادیار گروه برق، واحد بوشهر، دانشگاه آزاد اسلامی، بوشهر، ایران

چکیده

در این مقاله به بررسی جامعی از چگونگی رفتار نشست ولتاژ کنترل در اسیلاتورهای کنترل شده با ولتاژ(VCO) با در نظر گرفتن همه عوامل غیرایده‌آل در مدارهای حلقه قفل فاز پرداخته شده است. همچنین ساختارهای مختلف آشکار ساز فاز و تاثیر آنها بر روی سرعت قفل شدن مدار حلقه قفل فاز، ریپل ولتاژ کنترل و محدوده فرکانسی قفل با هم مقایسه خواهد شد. سه مدار حلقه قفل فاز با آشکاز فاز XOR، آشکارساز RS-FF و آشکارساز فاز دینامیکی در این مقاله بررسی شدند. شبیه سازیها در تکنولوژی 0.18µm-CMOS و با منبع تغذیه 1.8v انجام شد. نتایج شبیه سازی نشان می‌دهد محدوده عمل مدار حلقه قفل فاز شامل آشکار فاز دینامیکی با مدار پمپ بار نسبت به اثرات غیرایده‌آل نسبت به مدار حلقه قفل فاز شامل آشکار فاز XOR و مدار حلقه قفل فاز شامل آشکار فاز RS-FF ریپل کمتری دارد.

واژه های کلیدی :حلقه قفل فاز، آشکارساز فاز، اسیلاتور کنترل شده با ولتاژ

کلیدواژه‌ها

حلقه قفل فاز؛ آشکارساز فاز؛ اسیلاتور کنترل شده با ولتاژ

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