Design of Fault-Tolerant XOR/XNOR Gate Using Fault-Tolerant NNI Gate

International Journal of Smart Electrical Engineering

دوره 12، شماره 03، آذر 2023، صفحه 229-235   

نوع مقاله: Research Paper

شناسه دیجیتال (DOI): 10.30495/ijsee.2022.1935935.1126

نویسندگان

Fatemeh Kiayi¹؛ Behnaz Gharekhanlou^{* 2}؛ Alireza Kashaninya³

¹Department of Electrical Engineering, Central Tehran Branch, Islamic Azad University, Tehran, Iran

²Department of Electrical Engineering, Central Tehran Branch, Islamic Azad University, Tehran, Iran.

³Electrical Engineering Department, Central Tehran Branch, Islamic Azad University, Tehran, Iran

چکیده

Today more than ever, we need high-speed circuits with low occupancy and low power as an alternative to CMOS circuits. Therefore, we proposed a new path to build nanoscale circuits such as Quantum-dot Cellular Automata (QCA). This technology is always prone to failure due to its very small size. Therefore, designers always try to design fault-tolerant gates and provide methods to increase the reliability of QCA. By adding redundant cells, the possibility of some defects such as cell omission and cell addition is somewhat reduced. However, in the face of defects such as stuck-at 0/1 faults, Clock fault and bridging fault. We can greatly increase the fault tolerance by appropriate placement and using fault tolerant gates with a suitable structure. In this paper, we design the XOR/XNOR gate with the approach of preventing stuck-at 0/1 fault, clock fault, and bridging fault using the first NNI gate tolerating cell addition fault.

کلیدواژه‌ها

Quantum-dot Cellular Automata؛ Fault-tolerant XOR gate؛ Fault-tolerant XNOR gate؛ Fault-tolerant NNI؛ Clock defect؛ bridging defect؛ stuck at 0/1 defect