Design of Binary-to-Quaternary Converters based on CNTFET Transistors

Majlesi Journal of Electrical Engineering

مقاله 7، دوره 18، شماره 1، خرداد 2024، صفحه 65-73   

نوع مقاله: Reseach Article

شناسه دیجیتال (DOI): 10.30486/mjee.2023.1987201.1150

نویسندگان

maryam ghelichkhani¹؛ Seied Ali Hosseini^{* 2}؛ Seyyed Hossein Pishgar Komleh³؛ Alireza Siadatan⁴

¹Department of Electrical Engineering, College of Technical & Engineering, West Tehran Branch, Islamic Azad University

²Department of Electronic, College of Electrical Engineering, Yadegar-e-Imam Khomeini(RAH) Shahre Rey Branch, Islamic Azad University

³Department of Electrical Engineering, College of Technical & Engineering, West Tehran Branch, Islamic Azad University

⁴Department of Electrical Engineering, College of Technical & Engineering, West Tehran Branch, Islamic Azad University, Tehran, Iran

چکیده

In order to connect two binary and quaternary systems, it is necessary to use binary-to-quaternary (B2Q) and quaternary-to-binary (Q2B) converters. These converters convert numbers from logic 2 to 4 and vice versa.  In this paper, we designed a new binary-to-quaternary converter circuit using CNT transistors. In this circuit, the Power Delay Product (PDP) has been reduced to14.59% and 15.39% compared to best previous works (Ref [22] and Ref [23]). Also, this circuit has better driving ability and temperature stability than best previous works. The simulation results using Stanford's 32 nm CNTFET model in HSPICE software are at a voltage of 0.9 V.

کلیدواژه‌ها

CNTFET؛ Multi-Level Circuit؛ B2Q Converter؛ Mixed Radix System

مراجع

• C. Balla, A. Antoniou, “Low power dissipation MOS ternary logic family,” IEEE J. Solid-State Circuits, 19, (5), pp. 739–749,1984.
• Yoosefi Nejad, M. Mosleh “A Review on QCA Multiplexer Designs,” Majlesi Journal of Electrical Engineering, Vol. 11, (5), no.2, 2017.
• Mishra, S.H. Akashe, “High performance, low power 200 Gb/s 4:1 MUX with TGLin 45 nmtechnology,” Appl. Nanosci, 2014.
• Avouris, J. Appenzeller, R. Martel, S.J. Wind, “Carbon nanotube electronics,” IEEE Proc, 91, pp.1772–1784, 2003.
• Lin, Y. Kim, F. Lombardi, “CNTFET-based design of ternary logic gates and arithmetic circuits,” IEEE Trans. Nanotechnol, Vol. 10, No. 2, pp. 217–225, 2011.
• V. RatanKumar, L. Koteswara Rao and M. Kiran Kumar, “Design of Ternary Logic Circuits using Pseudo N-type CNTFETs,” ECS Journal of Solid State Science and Technology, 2022.
• Shahangian, S.A. Hosseini, R. Faghih Mirzaee “A Universal Method for Designing Multi-Digit Ternary to Binary Converter Using CNTFET,” Journal of Circuits, Systems, and Computers. 2020.
• Bolourforoush, M. Mohammadi Ghanatghestani, “A New Quaternary Full Adder Cell based on CNFET for Use in Fast Arithmetic Circuits,” ECS J. Solid State Sci. Technol., 11, 9, 2022.
• Daraei, S.A. Hosseini, “Novel energy-efficient and high-noise margin quaternary circuits in nanoelectronics,” AEU Int. J. Electron. Commun, 105, 145–162, 2019.
• Roosta, S.A. Hosseini, “A novel multiplexer-based quaternary full adder in nanoelectronics,” Circuits Syst. Signal Process, 38, pp. 4056–4078, 2019.
• Shahrom, S.A. Hosseini, “A new low power multiplexer based ternary multiplier using CNTFETs,” AEU Int. J. Electron. Commun, 93, pp. 191–207, 2018.
• Gadgil, CH. Vudadha, “Design of CNFET-based Low-Power Ternary Sequential Logic circuits,” IEEE 21st International Conference on Nanotechnology (NANO), 2022.
• Nemati, M. Haghi Kashani, R. Faghih Mirzaee, “Comprehensive survey of ternary full adders: Statistics, corrections, and assessments,” IET Circuits, Devices& Systems, 2023.
• Hajizadeh Bastani, M. H. Moaiyeri, K. Navi, “An Energy and Area Efficient Approximate Ternary Adder Based on CNTFET Switching Logic,” Circuits, Sys. Signal Processing, 37, No. 5, pp. 1863-1883, 2018.
• Rahbari, S.A Hosseini, “Novel ternary D-flip-flap-flop and counter based on successor and predecessor in nanotechnology,” AEU Int. J. Electron. Commun, 109, pp. 107–120, 2019.
• A. Hosseini, S. Etezadi, “A novel very low-complexity multi-valued logic comparator in nanoelectronics,” Circuits Syst. Signal Process, 39, pp. 223–244, 2020.
• Appenzeller, “Carbon nanotubes for high-performance electronics - Progress and prospect,” Proc IEEE, 96:201–11, 2008.
• L. McEuen, M.S. Fuhrer, H. Park, “Single-walled carbon nanotube electronics,” IEEE Transactions on Nanotechnology, pp.78-85, 2002.
• Deng, H. S.P Wong, “A compact SPICE model for carbon-nanotube field-effect transistors including non-idealities and its application—Part II: full device model and circuit performance benchmarking,” IEEE Trans. Electron. Device, 54(12), 3195–3205, 2007.
• Rasmita, S. Sahoo, K. Krishna Chaitanya Sankisa, “Design of an efficient CNTFET using optimum number of CNT in channel region for logic gate implementation,”IEEE Conference Publications, pp.1-4, 2015.
• L.Hurst, “Multiple-valued logic, its status and its future,” IEEE Transactions on computers, 1984.
• A. Ebrahimi, M. R. Reshadinezhad, A. Bohlooli, M. Shahsavari, “Efficient CNTFET-based design of quaternary logic gates and arithmetic circuit,”Microelectronic Journal, 53, pp.156-166, 2016.
• Ghelichkhani, S. A.Hosseini, S. H. Pishgar Komleh, “Multi-digit Binary-to-Quaternary and Quaternary-to-Binary Converters and Their Applications in Nanoelectronics,” AEU Int. J. Electron. Commun, 39(4), pp. 1920 - 1942, 2019.
• Liang, L.Chen,J.Han, F.Lombardi, “Design and evaluation of multiple valued logic gates using pseudon-type carbon nano tube FETs,” IEEETrans.Nano- technol. 695–708,2014.
• CNFET Model. http://nano.stanford.edu/models
• Kajal, Vijay Kumar Sharma, “An efficient low power method for Fin FET domino OR logic circuit,” Microprocessors and Microsystems, 2022, https://doi.org/10.1016/j.micpro.2022.104719.
• H. Moaiyeri, A. Doostaregan, K. Navi, “Design of energy-efficient and ternary circuits for nanotechnology,” IET Circ Dev Syst, 5(4):285296, 2011.
• Sharma, L. Kumre, “Design of low power multi-ternary digit multiplier in CNTFET technology,” Microprocessors and Microsystems, 73, 2020.
• F. Mirzaee, M.H. Moaiyeri, K. Navi, “dramatically low-transistor-count high-speed ternary adders,” in: 43rd Int. Symp. On Multi Valued Logic, pp. 170–175, 2013.