- J Lindroos, A. Lehto, T. Motooka, and M. Tilli, “Handbook of Silicon Based MEMS Materials and Technologies”. 2010.
- G. Croissant, K. S. Butler, J. I. Zink, and C. J. Brinker, “Synthetic amorphous silica nanoparticles: toxicity, biomedical and environmental implications,” Nat. Rev. Mater., vol. 5, no. 12, pp. 886–909, 2020, doi: 10.1038/s41578-020-0230-0.
- Paulasto-Kroâckel, M. Tilli, G. Ross, and H. Kuisma, “Where is silicon based MEMS heading to? Handbook of Silicon Based MEMS Materials and Technologies”. pp. xxi–xxix, 2020, doi: 10.1016/B978-0-12-817786-0.00062-1.
- Control and C. July, “Surface Position Detection Method of Silicon Melt in CZ Furnace,” pp. 5021–5026, 2016.
- Zhao, X. Zhao, M. Roders, A. Gumyusenge, A. L. Ayzner, and J. Mei, “Melt-Processing of Complementary Semiconducting Polymer Blends for High Performance Organic Transistors,” Adv. Mater., vol. 29, no. 6, pp. 1–7, 2017, doi: 10.1002/adma.201605056.
- Inoue et al., “Morphological characterization and mechanical behavior by dicing and thinning on direct bonded Si wafer,” J. Manuf. Process., vol. 58, no. January, pp. 811–818, 2020, doi: 10.1016/j.jmapro.2020.08.050.
- Inoue et al., “Influence of Si wafer thinning processes on (sub)surface defects,” Appl. Surf. Sci., vol. 404, pp. 82–87, 2017, doi: 10.1016/j.apsusc.2017.01.259.
- Shen, X. Zhu, J. Chen, P. Tao, and X. Wu, “Investigation on the edge chipping in ultrasonic assisted sawing of monocrystalline silicon,” Micromachines,” vol. 10, no. 9, 2019, doi: 10.3390/mi10090616.
- Takyu et al., “A Novel Dicing Technologies for WLCSP Using Stealth Dicing through Dicing Tape and Back Side Protection-Film,” Proc. - Electron. Components Technol. Conf., vol. 2016-Augus, pp. 1241–1246, 2016, doi: 10.1109/ECTC.2016.138.
- Xue, C. Zhong, E. Zhang, W. Jiang, and C. Zhang, “Die chipping FDC development at wafer saw process,” 2021 22nd Int. Conf. Electron. Packag. Technol. ICEPT 2021, 2021, doi: 10.1109/ICEPT52650.2021.9568039.
- Xue, T. Chen, X. Zhang, L. Gao, and M. Li, “Effect of Blade dicing parameters on Die Strength,” Proc. - 2018 19th Int. Conf. Electron. Packag. Technol. ICEPT 2018, pp. 180–183, 2018, doi: 10.1109/ICEPT.2018.8480532.
- Zhang, W. F. Wang, and P. Y. Huang, “Optimization of Wafer Dicing-Saw to Reduce the Chipping Defect by Using the Response Surface Methodology,” 2022 China Semicond. Technol. Int. Conf. CSTIC 2022, pp. 24–27, 2022, doi: 10.1109/CSTIC55103.2022.9856868.
- J. Su, Y. F. Chen, J. C. Cheng, and C. L. Chiu, “An artificial neural network approach for wafer dicing saw quality prediction,” Microelectronics Reliability, vol. 91. pp. 257–261, 2018, doi: 10.1016/j.microrel.2018.10.013.
- J. Kim, “Development of waxless wafer mounting system for silicon wafer polishing process,” Appl. Mech. Mater., vol. 339, pp. 762–765, 2013, doi: 10.4028/www.scientific.net/AMM.339.762.
- K. Bin Zainal, A. Bin Abdul Aziz, and V. Ramalingam, “Backside Chipping Investigation & Improvement on TiNiVAg Back Metal Silicon Die,” Proc. IEEE/CPMT Int. Electron. Manuf. Technol. Symp., vol. 2022-Octob, pp. 0–3, 2022, doi: 10.1109/IEMT55343.2022.9969494.
- A. Mendoza, A. G. S. Gablan, H. L. Tierra, and F. R. I. Gomez, “Process Simplification on Integration of UV Cure Machine with Tape Saw Singulation,” J. Eng. Res. Reports, vol. 20, no. 10, pp. 1–5, 2021, doi: 10.9734/jerr/2021/v20i1017382.
- P. Orlando, J. L. Goodrich, and E. L. Gosselin, “Backside Mounting Procedures for Semiconductor Wafer Processing,” 2001.
- S. Premachandran et al., “Wafer level high temperature reliability study by backside probing f or a 50um thin TSV wafer,” Proc. - Electron. Components Technol. Conf., vol. 2015-July, pp. 2144–2148, 2015, doi: 10.1109/ECTC.2015.7159899.
- C. S. Bacquian, “Dicing before Grinding : A Robust Wafer Thinning and Dicing Technology,” vol. 11, no. 4, pp. 25–34, 2020, doi: 10.9734/JERR/2020/v11i417067.
- Fabiana Meijon Fadul, “Analysis of Crystalline in GaN Epitaxial Layer after the Wafer Dicing Process,” vol. 1593, pp. 1–6, 2019.
- Sekhar et al., “Mechanical strength problem of thin silicon wafers (120 and 140 μm) cut with thinner diamond wires (Si kerf 120 → 100 μm) for photovoltaic use,” Materials Science in Semiconductor Processing, vol. 119. 2020, doi: 10.1016/j.mssp.2020.105209.
- Liu, T. Yang, X. Tian, S. Chen, F. Dong, and J. Han, “Iterative method for obtaining nonuniform grinding-induced residual stress distribution of silicon wafers based on global deformation,” Mater. Sci. Semicond. Process., vol. 150, no. July, p. 106971, 2022, doi: 10.1016/j.mssp.2022.106971.
- M. Chang and H. M. Ler, “Effect of Wafer Back Metal Thickness and Surface Roughness towards Backend Assembly Processes,” Proc. IEEE/CPMT Int. Electron. Manuf. Technol. Symp., vol. 2022-Octob, 2022, doi: 10.1109/IEMT55343.2022.9969478.
- Sekhar, T. Fukuda, K. Tanahashi, and H. Takato, “The impact of silicon brick polishing on thin (120 μm) silicon wafer sawing yields and fracture strengths in diamond-wire sawing,” Mater. Sci. Semicond. Process., vol. 105, no. September 2019, p. 104751, 2020, doi: 10.1016/j.mssp.2019.104751.
- Wu, F. Ren, and H. Ma, “The effect of surface morphology on the peel performance of UV-induced adhesion-reducing adhesives The effect of surface morphology on the peel performance of UV- induced adhesion-reducing adhesives,” 2022.
- Liu, Y. Wei, J. Wang, and S. Xu, “Investigation of single cut process in mechanical dicing for thick metal wafer,” 2016 17th Int. Conf. Electron. Packag. Technol. ICEPT 2016, pp. 26–30, 2016, doi: 10.1109/ICEPT.2016.7583083.
- Gao, R. Kang, Z. Dong, and B. Zhang, “Edge chipping of silicon wafers in diamond grinding,” International Journal of Machine Tools and Manufacture, vol. 64. pp. 31–37, 2013, doi: 10.1016/j.ijmachtools.2012.08.002.
- Y. Tsai and P. S. Huang, “Correction factors to strength of thin silicon die in three- and four-point bending tests due to nonlinear effects,” Microelectron. Reliab., vol. 128, no. September 2021, p. 114424, 2022, doi: 10.1016/j.microrel.2021.114424.
- Talledo, “Comparison of Silicon Die Strength Using Different Loading Anvil Shapes,” J. Eng. Res. Reports, vol. 20, no. 6, pp. 17–23, 2021, doi: 10.9734/jerr/2021/v20i617323.
- Talledo, “Effect of Silicon Die Condition on the Breaking Load Performance of a Dam and Fill Semiconductor Package,” J. Eng. Res. Reports, vol. 20, no. 6, pp. 64–69, 2021, doi: 10.9734/jerr/2021/v20i617328.
- E. Nikitin et al., “Fracture strength of silicon solar wafers with different surface textures,” Mater. Sci. Semicond. Process., vol. 140, no. November 2021, p. 106386, 2022, doi: 10.1016/j.mssp.2021.106386.
- N. Li, T. B. Yu, L. Da Zhu, and W. S. Wang, “Analytical modeling of ground surface topography in monocrystalline silicon grinding considering the ductile-regime effect,” Arch. Civ. Mech. Eng., vol. 17, no. 4, pp. 880–893, 2017, doi: 10.1016/j.acme.2017.03.010.
|