A Hybrid Forward/Reverse Converter in Reversible Logic to Reduce Hardware Complexity of Residual Number System

Majlesi Journal of Electrical Engineering

مقاله 3، دوره 18، شماره 2، شهریور 2024، صفحه 1-15   

نوع مقاله: Reseach Article

شناسه دیجیتال (DOI): 10.57647/j.mjee.2024.1802.29

چکیده

As an emerging technology, reversible computing enables the development of high-performance computing systems with low energy consumption. A residue number system (RNS) that performs arithmetic operations in parallel with error tolerance and no carry propagation requires forward and reverse converters to communicate with other digital circuits. Designing reversible forward and reverse converters using new technologies is very important due to their wide applications in implementing the RNS. These converters, which are the overhead of the system, increase energy consumption. This study proposes a hybrid converter conforming to reversible logic for the RNS. This hybrid converter unifies forward and reverse converters by sharing hardware and reversible gates. By using the mixed-radix conversion (MRC), the reverse conversion arithmetic relations adopt a similar format to that of the forward conversion arithmetic relations, and by the addition of a number of Fredkin gates and modifying the inputs, the reverse converter hardware is used to perform forward conversion. Based on the findings, the hybrid converter, which conformed to reversible logic for the moduli set {2^2n,2^n-1,2^(n+1)-1} and {2^n-1,2^n+1,2^2n+1}, decreased the quantum cost to 19.56% and 19.52%, respectively. 

کلیدواژه‌ها

Arithmetic Digital Circuits؛ Computer Arithmetic؛ Forward Converter؛ Moduli Adder؛ Residue Number System (RNS)Reverse Converter

مراجع

[1] L. S. a. C. C. A. S. Molahosseini. “embedded systems design with special arithmetic and number
systems.”. Springer International Publishing, , 2017.
[2] B. Moons, D. Bankman, and M. Verhelst. “embedded
deep neural networks.”. Embedded Deep Learning:
Algorithms, Architectures and Circuits for Always-on
Neural Network Processing, :pp. 1–31, 2019.
[3] L. Sousa, S. Antao, and P. Martins. “combining
residue arithmetic to design efficient cryptographic
circuits and systems.”. IEEE Circuits and Systems
Magazine, 16:pp. 6–32, 2016.
[4] H. Garner. “the residue number system.”. IRE Transaction on Electronic Computer, 8:pp. 140–147, 1959.
[5] M. Mojahed, A. S. Molahossein, and A. A. Emrani
Zarandi. “magnitude comparison and sign detection based on the 4-moduli set {2
n +1, 2
n −1, 2
n +
3, 2
n −3}.”. Majlesi Journal of Electrical Engineering, 15:pp. 93–103, 2021.
[6] C. H. Chang, A. S. Molahosseini, A. A. E. Zarandi,
and T. F. Tay. “residue number systems: a new
paradigm to datapath optimization for low-power
and high-performance digital signal processing applications.”. IEEE circuits and systems magazine, 15
(6):pp. 26–44, 2015.
[7] T. M. Conte, E. P. DeBenedictis, P. A. Gargini, and
E. Track. “rebooting computing: the road ahead. ”.
Computer, 50:pp. 20–29, 2017.
[8] H. A. Mousavi, P. Keshavarzian, and A. S. Molahosseini. “a novel fast and small xor-base fulladder in quantum-dot cellular automata. ”. Applied
Nanoscience, :pp. 4037–4048, 2020.
[9] A. Asadpour, A. S. Molahosseini, and A. A. E.
Zarandi. “the use of reversible logic gates in
the design of residue number systems.”. International Journal of Electrical and Computer Engineering (IJECE), 13:pp. 2009–2022, 2023.
[10] A. S. Molahosseini, A. Asadpoor, A. A. E. Zarandi,
and L. Sousa. “towards efficient moduliadders
based on reversible circuits.”. in International Symposium on Circuits and Systems (ISCAS), IEEE, 12:
pp. 1–5, 2018.
[11] A. Asadpour, A. S. Molahosseini, and A. A. E.
Zarandi. “the use of reversible logic gates in
the design of residue number systems.”. International Journal of Electrical and Computer Engineering (IJECE), 13:pp. 2009–2022, 2023.
[12] A. Peres. “reversible logic and quantum computers.”. Physical review A, 32:pp. 3266, 1985.
[13] E. Fredkin and T. Toffoli. “quantum mechanical
computers.”. Int. J. Theor. Phys, 21:pp. 219–253,
1982.
[14] S. M. R. Taha. “reversible logic synthesis methodologies with application to quantum computing.”.
Springer, 16, 2016.
[15] E. P. DeBenedictis, J. K. Mee, and M. P. Frank. “the
opportunities and controversies of reversible computing.”. Computer, 50:pp. 76–80, 2017.
[16] B. Deng, S. Srikanth, E. Hein, T. M. Conte, E. Debenedictis, J. Cook, and M. P. Frank. “extending moore’s
law via computationally error-tolerant computing.”. ACM Transactions on Architecture and Code
Optimization (TACO), 15:pp. 1–27, 2018.
[17] H. Sinha and N. Syal. “design of fault tolerant reversible multiplier.”. International Journal of Soft
Computing and Engineering (IJSCE), 1:pp. 120–124,
2012.
[18] N. K. Misra, M. K. Kushwaha, S. Wairya, and A. Kumar. “cost efficient design of reversible adder circuits for low power applications.”. arXiv preprint, :
pp. 1509–04618, 2015. [19] M. B. Ali, H. A. Rahman, and M. M. Rahman. “design
of a high performance reversible multiplier.”. International Journal of Computer Science Issues (IJCSI),
8:pp. 134, 2011.
[20] A. S. Molahosseini, A. A. E. Zarandi, P. Martins, and
L. Sousa. “a multifunctional unit for designing
efficient rns-based datapaths.”. IEEE Access, 54:pp.
25972–25986, 2017.
[21] M. Mojahed, A. S. Molahosseini, and A. A. E. Zarandi.
“multifunctional unit for reverse conversion and
sign detection based on five-moduli set {2
2n
,2
n +
1,2
n −1,2
n +3,2
n −3}.”. Computer Science, 22:pp.
101–121, 2021.
[22] P. M. M. Matutino, R. Chaves, and L. Sousa.
“arithmetic-based binary-to-rns converter modulo
2n ± k jn-bit dynamic range.”. IEEE Transactions
on Very Large Scale Integration (VLSI), 23:pp. 603–
607, 2015.
[23] M. Haghparast and K. Navi. “a novel reversible bcd
adder for nanotechnology based systems.”. IAmerican Journal of Applied Sciences, 5:pp. 282–288, 2008.
[24] A. S. molahosseini, C. Dadkhah, K. Navi, and M. Eshghi. “efficient mrc-based residue to binary converters for the new moduli sets {22n
,2
n −1,2
n+1 −1}
and {22n
,2
n −1,2
n−1 −1}.”. IEICE transactions on
information and systems, 9:pp. 1628–1638, 2009.
[25] A. S. Molahosseini, K. Navi, C. Dadkhah, O. Kavehei,
and S. Timarchi. “efficient reverse converter designs
for the new 4-moduli sets {2
n–1,2
n
,2
n+1,2
2n+1–1}
and {2
n–1,2
n +1,2
2n
,2
2n +1} based on new crts.”.
IEEE Transactions on Circuits and Systems I: Regular
Papers, 57:pp. 823–835, 2009.
[26] A. Emrani Zarandi and A. Sabbagh Molahosseini.
“hybrid design of forward and reverse converters:
a new approach to reduce hardware complexity of
residue number system.”. TABRIZ JOURNAL OF
ELECTRICAL ENGINEERING, 50:pp. 1315–1328,
2020.
[27] B. K. Raju, P. R. Kumar, and P. B. Rao. “residue
arithmetic’s using reversible logic gates.”. International Conference on Devices, Circuits and Systems
(ICDCS),IEEE, :pp. 1–6, 2014.
[28] S. Shirahatti, R.Shettar, R.Hongal, and U.Malenahalli.
“performance analysis of rns arithmetic operations
using reversible logic.”. International Conference on
Emerging Research in Electronics, Computer Science
and Technology (ICERECT),IEEE, :pp. 1–5, 2022.
[29] M. Mohammadi and M. Eshghi. “on figures of merit
in reversible and quantum logic designs.”. Quantum
Information Processing, 8:pp. 297–318, 2009.
[30] M. Arabzadeh and M. Saeedi. “rcviewer +: a viewer/analyzer for reversible and quantum circuits.”. ,
2018.