FPGA-accelerated bird detection algorithm for paddy farmers

Majlesi Journal of Electrical Engineering

دوره 19، شماره 3، آذر 2025، صفحه 1-11   

نوع مقاله: Reseach Article

شناسه دیجیتال (DOI): 10.57647/j.mjee.2025.17276

نویسندگان

Muhammad Ili Firdaus Mohamad Sa’ad¹؛ Rizalafande Che Ismail^{* 2، 3}؛ Siti Zarina Md Naziri^{2، 3}؛ Mohd Nazrin Md Isa^{2، 3}؛ Ahmad Husni Mohd Shapri^{2، 3}

¹Altera Corporation, Bayan Lepas Technoplex, 11900 Penang, Malaysia.

²Centre of Excellence for Micro System Technology, Universiti Malaysia Perlis, 02600 Perlis, Malaysia.

³Faculty of Electronic Engineering & Technology, Universiti Malaysia Perlis, 02600 Perlis, Malaysia.

چکیده

Paddy farmers face significant challenges from bird pests, particularly species such as pipits and sparrows, which can reduce yields by up to 70%, especially during the grain-filling stage, leading to substantial economic losses. Traditional pest control methods such as physical barriers, scare tactics, and chemical deterrents are often inefficient and labour-intensive. To address this issue, this research develops an artificial intelligence (AI)-based bird detection system to protect paddy fields. The solution involves using a Field-Programmable Gate Array (FPGA)-accelerated object detection model to accurately identify bird activity in real time. The system integrates a notification mechanism via Telegram to alert farmers immediately, enabling swift manual intervention. The research employed the DEtection TRansformer with ResNet-50 backbone (DETRResNet50) model for its precision and high confidence in detection, running on both Central Processing
Unit (CPU) and FPGA configurations to optimize performance. Results showed significant improvements in latency and frames per second (FPS) when using FPGA acceleration, demonstrating effective real-time bird detection capabilities. The system’s implementation enhanced crop protection, promoted eco-friendly practices, and improved overall farming efficiency by reducing manual surveillance and providing valuable data for long-term pest management strategies. Key quantitative findings revealed that FPGA acceleration improved FPS by over 200% compared to CPU performance.

کلیدواژه‌ها

Artificial intelligence؛ FPGA؛ Object detection model؛ Smart farming؛ Image processing

مراجع

[1] Y. Wang, Y. Liao, Y. Yang, J. Wang, and H. C Zhao. “An FPGAbased Online Reconfigurable CNN Edge Computing Device for Object Detection.”. Microelectronics J, 137:105805, 2023. DOI: https://doi.org/10.1016/j.mejo.2023.105805.
[2] A. Osman Hashi, A. A. Abdirahman, M. Abdirahman Elmi, O. Ernest, and R. Rodriguez. “Deep Learning Models for Crime Intention Detection Using Object Detection.”. Int. J. Adv. Comput. Sci. Appl., 14(4):1–20, 2023. DOI: https://doi.org/10.14569/ijacsa.2023.0140434.
[3] B. Razali. “Pengurusan burung perosak di sawah padi (Management of Bird Pests in Rice Field).”. Buletin Teknologi MARDI Bil, 34:29–44, 2022.
[4] Z. Li. “Investigation of Reconfigurable Hardware Acceleration for Low-Power Embedded Neural Networks.”. Universit´e Cˆote d’Azur, Theses De Doctorat, 2024.
[5] C. Vasile and A. Ulm. “Image Processing Hardware Acceleration — A Review of Operations Involved and Current Hardware Approaches.”. Journal of Imaging, 10(12):298, 2011. DOI: https://doi.org/10.3390/jimaging10120298.
[6] A. D. Santi. “Reducing Latency of Object Detection Systems Using Bayer Filters Reducing Latency of Object Detection Systems Using Bayer Filters.”. KTH, School of Electrical Engineering and Computer Science Dissertation (Master), 2024.
[7] P. Xiyuan, Y. Jinxiang, Y. Bowen, and L. Liansheng. “A Review of FPGA-Based Custom Computing Architecture for Convolutional Neural Network Inference.”. Chinese Journal of Electronics, 30 (1):1–17, 2021. DOI: https://doi.org/10.1049/cje.2020.11.002.
[8] N. Carion, F. Massa, G. Synnaeve, N. Usunier, A. Kirillov, and S. Zagoruyko. “End- to-End Object Detection with Transformers.”. European Conference on Computer Vision, pages 213–229, 2020. DOI: https://doi.org/10.1109/access.2022.3208889.
[9] K. Zeng, Q. Ma, J. W. Wu, Z. Chen, T. Shen, and C. Yan. “FPGAbased Accelerator for Object Detection: A Comprehensive Survey.”. Journal of Supercomputing, 78(12):14096–14136, 2022. DOI: https://doi.org/10.1007/s11227-022-04415-5.
[10] A. Montgomerie-Corcoran, P. Toupas, Z. Yu, and C. S. Bouganis. “SATAY: A Streaming Architecture Toolflow for Accelerating YOLO Models on FPGA Devices.”. Proceedings-International Conference on Field-Programmable Technology, ICFPT, page 179–187, 2023. DOI: https://doi.org/10.1109/icfpt59805.2023.00025.
[11] X. Zhou, D. Wang, and P. Kr¨ahenb¨uhl. “Objects as Points.”. arXiv preprint arXiv:1904.07850, 2019.
[12] Z. Yan, B. Zhang, and D. Wang. “An FPGA-Based YOLOv5 Accelerator for Real-Time Industrial Vision Applications.”. Micromachines (Basel), 15(9):1164, 2024. DOI: https://doi.org/10.3390/mi15091164.
[13] X. Li, Y. Wei, J. Li, W. Duan, X. Zhang, and Y. Huang. “Improved YOLOv7 Algorithm for Small Object Detection in Unmanned Aerial Vehicle Image Scenarios.”. Applied Sciences, 14(4):1664, 2024. DOI: https://doi.org/10.3390/app14041664.
[14] A. Bochkovskiy, C.-Y. Wang, and H.-Y. M. Liao. “YOLOv4: Optimal Speed and Accuracy of Object Detection.”. arXiv preprint arXiv:2004.10934, 2020.
[15] Peraka, Shyam, R. Sudheer, B. Narasimha Rao, A. R. Teja, and E. N. Kumar. “Smart irrigation based on crops using IoT.”. 15th International Conference on Industrial and Information Systems (ICIIS), pages 611–616, 2020. DOI: https://doi.org/10.1109/iciis51140.2020.9342736.
[16] C. Robinson. “Intel Arria 10 GX FPGA Card for Servers Released.”. URL https://www.servethehome.com/intel-arria-10-gx-fpga-card-for-servers-released/.
[17] E. Wovchena. “detr-resnet50.”. Github repository, 2022. URL https://github.com/openvinotoolkit/open model zoo/blob/master/models/public/detr-resnet50/README.md.
[18] Q. Murad, K. Denolf, J. Lo, K. Vissers, J. Zambreno, and P. H. Jones. “Comparing energy efficiency of CPU, GPU and FPGA implementations for vision kernels.”. IEEE International Conference on Embedded Software and Systems (ICESS), pages 1–8, 2019. DOI: https://doi.org/10.1109/icess.2019.8782524.
[19] Y. A. Gean and K. Ganesan. “Measuring the Power-Constrained Performance and Energy Gap between FPGAs and Processors.”. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 285–285, 2017. DOI: https://doi.org/10.1145/3020078.3021756.
[20] W. Tianwen. “yolo-v4-tf — OpenVINO.”. Github repository, 2020. URL https://github.com/TNTWEN/OpenVINO-YOLOV4/blob/master/yolo v4.py.
[21] A. Mironova. “ctdet coco dlav0 512.”. Github repository, 2020. URL https://github.com/openvinotoolkit/open model zoo/blob/master/tools/accuracy checker/configs/ctdet coco dlav0 512.yml.