A Single loop Feed Forward Sigma-Delta Modulator for GSM Standard

Majlesi Journal of Telecommunication Devices

مقاله 5، دوره 6، شماره 3، آذر 2017   

نوع مقاله: Articles

نویسندگان

Mohsen Beiranvand^* ؛ Ebrahim Rahimi؛ Gholamreza Babaabasi

چکیده

A sigma-delta modulator designed as part of a complete GSM (enhanced data rate for GSM evolution) transceiver is described. High-resolution wide-band analog-to-digital converters enable the receiver to rely on digital processing, rather than analog filtering, to extract the desired signal from blocking channels. High linearity and High SNR are the most stringent requirements for the converters in this wireless application. In this paper a second-order modulator with feed forward structure in order to cover bandwidth correspond to GSM telecommunication standards is designed and simulated. In this modulator, low distortion structure and according to the relevant standard bandwidth is used. In order to provide minimum GSM standard requirement parameters, a second – order modulator is used and by an oversampling rate of 120 and bandwidth of 200 KHZ, SNR, 98 dB and the accuracy of 15.5 bits is achieved. Also its circuit structure by using capacitance switch method with 0.13 micron technology and 1.8 volt power supply has been implemented.

کلیدواژه‌ها

Analog to Digital Converter؛ Sigma – Delta modulator؛ low – power components؛ low voltage

مراجع

[1] Ana Rusu , Hannu Tenhunen, A THIRD-ORDER SIGMA-DELTA MODULATOR FORDUAL-MODE RECEIVERS, Royal Institute of Technology Stockholm,Isafjordsgatan 39, SE-164 40 Kista, Sweden,2004.

[2] Ana Rusu1,2, Alexei Borodenkov1, Mohammed Ismail1,3 and Hannu Tenhunen1, Design of a Power/Performance Efficient Single-LoopSigma-Delta Modulator for Wireless Receivers, Royal Institute of Technology (KTH) Stockholm, IT-University/IMIT/ LECS/ESDlabIsafjordsgatan39, SE-16440 Kista, Sweden,2005.

[3] Andrea Xotta, Andrea Gerosa, Andrea Neviani, A Multi-Mode Analog-to-Digital Converter for GSM, UMTS and WLAN, IEEE J. of Solid-State Circuits, Vol. 38, No. 3, pp.464-474,2005.

[4] C-Y. Ho, et al., “A 4.5mW CT self-coupled ΔΣmodulator with 2.2MHz BW and 90.4dB SNDRusing residual ELD compensation,” ISSCC Dig.Tech. Papers, pp. 274–276, Feb. 2015.

[5] R.Ganesh Raj, A.Karmakar, S.C.Bose, “Analysis and design of 2nd order sigma-delta modulator for audio applications”, IEEE tran.Inf.theory, vol.8,no.10,pp.828-832,oct.2014.

[6] J. Borg and J. Johansson, “An ultrasonic transducer interface IC with integrated push-pull 40 Vpp, 400 mAcurrent output, 8-bit DAC andintegrated HV multiplexer,” IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 475–484, Feb. 2011.

[7] Yao Liu, Edoardo Bonizzoni, Alessandro D’Amato, and Franco Maloberti. A 105-dB SNDR, 10 kSps multi-level second-order incremental converter with smart-DEM consuming 280 μW and 3.3-V supply. In European Solid State Circuits Conference, pages 371–374, September 2013.

[8] Wenhuan Yu, Mehmet Aslan, and Gabor C Temes. 82 dB SNDR 20-Channel Incremental ADC with Optimal Decimation Filter and Digital Correction. In IEEE Custom Integrated Circuits Conference, pages 1 – 4, 2010.

[9] Julian Garcia, Saul Rodriguez, and Ana Rusu. A Low-Power CT Incremental 3rd Order ADC for Biosensor Applications. IEEE Transactions on Circuits and Systems I: Regular Papers, 60(1):25–36, 2012.

[10] Fabio Sebastiano and Robert H M Van Veldhoven. A 0.1-mm 3-Channel Area-Optimized ADC in 0.16-μm CMOS with 20-kHz BW and 86-dB DR. In European Solid State Circuits Conference, pages 375–378, 2013.

[11] Debasish Behera and Nagendra Krishnapura. A 2-Channel 1MHz BW, 80.5 dB DR ADC Using a Modulator and Zero-ISI Filter. In European Solid- State Circuits Conference, pages 415–418, 2014.

[12] JG Kauffman, Pascal Witte, Matthias Lehmann, and Joachim Becker. A72 dB DR, CT Modulator Using Digitally Estimated, Auxiliary DACLinearization Achieving 88 fJ/conv-step in a 25 MHz BW. IEEE Journal ofSolid-State Circuits, 49(2):392–404, 2014.

[13] R. Muller, H.-P. Le, W. Li, P. Ledochowitsch, S. Gambini, T. Bjorninen, A. Koralek, J.M. Carmena, M.M. Maharbiz, E. Alon, and J.M. Rabaey. A Minimally Invasive 64-Channel Wireless μECoG Implant. IEEE Journal ofSolid-State Circuits, 50(1):344–359, 2015.

[14] Taehoon Kim, N Sertac Artan, Jonathan Viventi, and H Jonathan Chao. Spatiotemporal Compression for Efficient Storage and Transmission of High- Resolution Electrocorticography Data. In Annual International Conference of the IEEE Engineering in Medicine and Biology Society, volume 2012, pages 1012–5, August 2012.

[15] A Rodriguez-Perez, M Delgado-Restituto, and F Medeiro. A 515 nW, 0-18 dB Programmable Gain Analog-to-Digital Converter for In-Channel Neural Recording Interfaces. IEEE Transactions on Biomedical Circuits and Systems,8(3):358–370, 2014.

[16] Kin-Sang Chio, Seng-Pan U 1 and R. P. Martins 2. A Dual-Mode Low-Distortion Sigma-Delta Modulator with Relaxing Comparator Accuracy, 0-7803-9390-2/06/$20.00 ©2006 IEEE.

[17] Li Hongyi(李宏义), Wang Yuan(王源)Ž, Jia Song(贾嵩), and Zhang Xing(张兴), An improved single-loop sigma–delta modulator for GSM applications, Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics, Peking University, Beijing 100871, China,

Vol. 32, No. 9, September 2011.