A Low Noise Amplifier with Low Voltage, Low Power Consumption, and Improved Linearity at 5 GHz

Majlesi Journal of Electrical Engineering

مقاله 10، دوره 11، شماره 1، خرداد 2017   

نوع مقاله: Review Article

نویسندگان

Amin Zafarian^{* 1}؛ Iraj Kalali Fard²؛ Abbas Golmakani³؛ Jalil Shirazi⁴

¹Electrical Engineering Department, Islamic Azad University Branch Of Arak, Iran

²RWTH Aachen University

³Department of Electrical Engineering, Sadjad University of Technology, Mashhad

⁴Electrical Engineering Department, Islamic Azad University Branch Of Gonabad, Iran Country Iran

چکیده

In this paper a low-noise amplifier with 0.6 V supply voltage, low power consumption, and improved linearity at= 5 GHz is introduced in 0.18 µm CMOS technology. By using a feed-forward structure and a multi-gated configuration in the proposed circuit, linearity of the circuit is significantly improved, while only 122 µW more power is consumed compared to conventional folded cascode structure, and the other circuit parameters are similar. In addition, the Volterra series is used for nonlinear analysis and to evaluate the linearity improvement of the proposed circuit. There is also a noteworthy superiority over compared published works in the figure of merit. The suggested low-noise amplifier (LNA) at 1.28 mW DC power consumption provides 9.6 dB gain and a noise figure of 3.24 dB. It is achieved whilst the third order interception point has been improved by 10 dB and equals 0.0 dBm. In the operating frequency the circuit displays satisfactory input and output impedance matching.  Finally, throughout the whole circuit bandwidth input and output isolation is below −27 dB.

کلیدواژه‌ها

en

مراجع

[1] Hsieh-Hung Hsieh and Liang-Hung Lu, “A CMOS 5-GHz micro-power lna”, IEEE Radio Frequency integrated Circuits (RFIC) Symposium, pp. 31-34, June 2005.

[2] A. Zafarian, I. Kalali Fard, A. Golmakani, and J. Shirazi, “A 0.4V 790µW CMOS low noise amplifier in sub-threshold region at 1.5GHz”, in Proceeding 8th International Design and Test Symposium (IDT), pp. 1-6, Marrakesh, Dec. 2013.

[3] Tae-Sung Kim, Byung-Sung Kim, “PostLinearization of Cascode CMOS Low Noise Amplifier Using Folded PMOS IMD Sinker”, IEEE Mi- crowave and Wireless Components Letters, Vol 16, No 4, pp. 182-184, April 2006.

[4] Chi-Wan Park, Jichai Jeong, “Consideration of Linearity in Cascode Low Noise Amplifiers using Double Derivative Superposition Method with a Tuned Inductor”, in Proceeding Microwave Conference, pp. 21-24, Korea- Japan, 2007.

[5] H.M Geddada, J.W. Park, J. Silva-Martinez, “Robust derivative superposi- tion method for linearising broadband LNAs ”, IEEE Electronics Letters, Vol 45, No 9, pp. 435-436, April 2009.

[6] V. Aparin, L.E. Larson, “Modified derivative

superposition method for linearizing FET low-noise amplifiers”, IEEE Transactions on Microwave Theory and Techniques, Vol 53, No 2, pp. 571-581, Feb 2005.

[7] S. Ganesan, E. Sanchez-Sinencio, J. SilvaMartinez, “A Highly Linear Low-Noise Amplifier”, IEEE Transactions on Microwave Theory and Techniques, Vol 54, No 12, pp. 4079-4085, Dec 2006.

[8] Donggu Im, Ilku Nam, Hong-Teuk Kim, Kwyro Lee, “A Wideband CMOS Low NoiseAmplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner ”, IEEE Journal of Solid-State Circuits, Vol 44, No 3, pp. 686- 698, March 2009.

[9] H. H. Hsieh, J. H. Wang, L. H. Lu, “GainEnhancement Techniques for CMOS Folded Cascode LNAs at Low-Voltage Operations”, IEEE Transactions on Microwave Theory and Techniques, Vol 56, No 8, pp. 1807-1816, Aug 2008.

[10] Heng Zhang, E. Sanchez-Sinencio, “Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial”, IEEE Transactions on Circuits and Systems, Part I: Regular Papers, Vol 58, No 1, pp. 22- 36, Jan 2011.

[11] Stephen A. Maas, “Nonlinear Microwave and RF Circuits, artech house publishers”, January 2003.

[12] Trung-Kien Nguyen, Chung-Hwan Kim, Gook-Ju Ihm, Moon-Su Yang, and Sang-Gug Lee, “CMOS Low-Noise Amplifier Design Optimization Techniques”, IEEE Transactions On Microwave Theory And Techniques, Vol 52, No 5, pp. 1433-1442, May 2004.

[13] Chunyu Xin, E. Sanchez-Sinencio, “A Linearization Technique For Rf Lownoise Amplifier”, Proceedings of the International Symposium on Circuits and Systems (ISCAS), pp. 313-316, May 2004.

[14] Hanil Lee, Saeed Mohammadi, “A 3GHz Subthreshold CMOS Low Noise Amplifier”, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, San Francisco CA, June 2006.

[15] Benqing Guo, Guangjun Wen, Shiquan An, “6.8 mW 15 dBm IIP3 CMOS common-gate LNA employing post-linearisation technique”, Elec- tronics Letters, Vol 50, No 3, pp. 149-151, January 2014.

[16] Yeo Myung Kim, Honggul Han, Tae Wook Kim, “A 0.6-V +4 dBm IIP3 LC Folded Cascode CMOS LNA With gm Linearization”, IEEE Transactions On Circuits And SystemsII: Express Briefs, pp. 122-126, Vol 60, No 3, March 2013.

[17] F. Eshghabadi, H.A. Eshghabadi, N.M. Noh, M.T. Mustaffa, “A low- power high-gain 2.45-GHz CMOS dual-stage LNA with linearity enhancement”, IEEE International Conference on Circuits and Systems (ICCAS), pp. 249-253, Kuala Lumpur, Oct 2012.

[18] Chia-Hung Chang, Tao Wang, C.F. Jou, “Dual cross-coupling LNA with forward body bias technique”, Electronics Letters, Vol 48, No 18, pp. 1100-1102, August 2012.

[19] J. Jiang, D.M. Holburn, “Design and analysis of a highly linear fully differential LNA for SOC”, 15th IEEE Mediterranean Electrotechnical Conference, pp. 300-303, Valletta, April 2010.