New Multiply-Accumulate Circuits Based on Variable Latency Speculative Architectures with Asynchronous Data Paths

Majlesi Journal of Electrical Engineering

مقاله 4، دوره 16، شماره 2، شهریور 2022، صفحه 41-53   

نوع مقاله: Review Article

شناسه دیجیتال (DOI): 10.30486/mjee.2022.696494

نویسندگان

Hoda Ghabeli¹؛ Amir Sabbagh Molahosseini^{* 1}؛ Azadeh Alsadat Emrani Zarandi²

¹Department of Computer Engineering, Kerman Branch, Islamic Azad University, Kerman, Iran.

²Department of Computer Engineering, Shahid Bahonar University of Kerman, Kerman, Iran.

چکیده

In this paper, variable latency speculative Multiply-Accumulator (MAC) architectures are introduced. The proposed architectures use the idea of integrating the results vectors of multiplier in parallel with the accumulator to create asynchronous data paths design. The proposed variable latency speculative MACs consist of two short and long data paths and a circuit is used to select a suitable path with minimum overhead. In order to investigate variable latency speculative MACs performances, proposed architectures have been synthesized using the Faraday’s 90 nm technology library, for operand lengths 8, 16 and 32 bits. Obtained results show that the proposed MAC architectures provide a variety of trade-offs in the power-delay-area space that outperform the existing designs that use only the integration technique.

کلیدواژه‌ها

Integration Technique؛ Multiply-Accumulator؛ Partial-Product؛ Variable Latency Speculative Circuits

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