Numerical optimization of threshold voltage and off-current of a nano-scale symmetric double gate MOSFET based on the genetic algorithm: Various strategies compatible with device applications

International Journal of Nano Dimension

مقاله 7، دوره 14، شماره 1، فروردین 2023، صفحه 91-102   

نوع مقاله: Reasearch Paper

شناسه دیجیتال (DOI): 10.22034/ijnd.2022.1963798.2166

نویسندگان

Yazdan Karimi Pashaki¹؛ Seyed Ali Sedigh Ziabari^{* 1}؛ Abdollah Eskandarian¹؛ Ali Rahnamaei²

¹Department of Electrical Engineering, Rasht Branch, Islamic Azad University, Rasht, Iran.

²Department of Electrical Engineering, Ardabil Branch, Islamic Azad University, Ardabil, Iran.

چکیده

In this paper, we optimize the electrical characteristics of Nano-scale symmetric double-gate metal oxide semiconductor field effect transistors (DG-MOSFETs) for digital applications using a genetic algorithm. We use a single-objective genetic algorithm to optimize the threshold voltage (V_th) with a distinct analytical relationship. The optimization of the threshold voltage is accomplished for three cases with considering two structural variables of the oxide thickness (t_ox), the channel thickness (t_si), and the channel doping density (N_a). The fourth case of optimization is done with considering these three variables. Comparison of these four cases illustrates that the best threshold voltage is 0.15 V for a channel doping concentration of 1.2×10 ¹⁰ cm^-3 and an oxide thickness of 1.49 nm. In addition, we optimize the OFF-current criterion based on the gate oxide thickness, the channel thickness, the channel doping concentration and the channel length and width. The optimization processes of the device are validated by simulating in SILVACO software. Furthermore, we use the two-objective genetic algorithm with the threshold voltage and the OFF-current objects for four structural variables including the gate oxide thickness, the channel layer thickness, and the channel length and width. This process is applicable to digital circuit design. To evaluate the accuracy of the proposed device optimization, the optimized device and other situations are simulated in SILVACO simulator. The optimized device illustrates the best treatment. 

کلیدواژه‌ها

Genetic Algorithm؛ Nano-Scale Double-Gate MOSFET؛ OFF-Current؛ Scaling؛ Threshold Voltage

مراجع

1. Elmessary M. A., Nagy D., Aldegunde M., Seoane N., Indalecio G., Lindberg J., Dettmer W., Peric D., García-Loureiro A. J., Kalna K., (2017), Scaling/LER study of Si GAA nanowire FET using 3D finite element Monte Carlo simulations: Scaling limits and opportunities. Solid-State Electronics. 128: 17-24.
2. Choi Y., Park B. G., Lee J. D., Liu T. J. K., (2007), Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60mV. IEEE. Elec. 28: 743–745.
3. Ebrahimnia M., Sedigh Ziabari S. A., Kiani-sarkaleh , (2022), Influence analysis of dielectric pocket on ambipolar behavior and high-frequency performance of dual material gate oxide stack-double gate Nano-Scale TFET. J. Nanoanalysis. Articles in Press.
4. Vimala, Balamurugan N. B., (2013), Modelling the centroid and charge density in double-gate MOSFETs including quantum effects. Int. J. Elec. 100: 1283-1295.
5. Ratnesh K., Goel A., Kaushik G., Garg H., Chandan., Singh M., Prasad B., (2021), Advancement and challenges in MOSFET scaling. Mater. Sci. Semi. Proc. 134: 106002.
6. Ionescu M., Riel H., (2011), Tunnel field-effect transistors as energy-efficient electronic switches. Nature. 479: 329-337.
7. Anghel, Chilagani P., Amara A., Vladimirescu A., (2010), Tunnel field effect transistor with increased on current, low-k spacer and high-k dielectric. AIP. Applied. Phys. Let. 96: 122104-1-3.
8. Cristoloveanu S., Wan, Zaslavsky A., (2016), A Review of sharp-switching devices for ultra-low power applications. IEEE. J. Elec. Dev. 4: 215-226.  
9. Aditya M., Srinivasa-Rao K., (2021), Design and performance analysis of advanced MOSFET structures. Elect. Electronic Mat. 23: 219-227.
10. Ferain I., Colinge C. A., Colinge J. P., (2011), Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors. 479: 310-316.
11. Sun Y., Yu U., Zhang R., Chen B., Cheng R., (2021), The past and future of multi-gate field-effect transistors: Process challenges and reliability issues. J. Semi. 42: 023102.
12. Anthony-Uchechukwu, M-Srivastava V., (2020), Channel length scaling pattern for cylindrical surrounding double-gate (CSDG) MOSFET. IEEE Access. 8: 121204-121210.
13. Sze M., (2002), Physics of semiconductor devices. Wiley-Inter science.
14. Kumar, Khiangte L., Sankar-Dhar R., (2020), Design of DG MOSFET with tri-layered strained silicon channel. J. Physics: Conf. Series. 1478: 012002.
15. Coquan R., Casse M., Barraud S., Cooper D., Alvaro V. M., Samson M. P., Mofray S., Boeuf F., Ghibaudo G., Faynot O., Poiroux T., (2012), Strain-induced performance enhancement  of tri-gate and omega-gate nanowire FETs scaled down to 10 nm width. 60: 727-732.
16. Khan , A-Loan S., (2020), Metal drain double-gate tunnel field effect transistor with underlap: Design and simulation. Silicon. 13: 1421-1431.
17. Djeffal F., Abdi M. A., Dibi D.,  Chahdi M.,  Benhaya A., (2008), A neural approach to study the scaling capability of the undoped double-gate and cylindrical gate all around MOSFETs. Sci. Eng. 147: 239-244.
18. Giuseppe A., Butera F., Nella R., (2014), Geometrical and physical optimization of a photovoltaic cell by means of genetic algorithm. Compu. Electron. 13: 323-328.
19. Parvane, Rahimi E., Jafarinejad F., (2020), Optimization of quantum cellular automata circuits by genetic algorithm. Int. J. Eng. 33: 229-236.
20. Liu W., Jin X., Xi X., Chen J., Jeng M., Liu Z., Cheng Y., Chen K., Chan M., Hui K., Huang J., Tu R., Ping-Ko K., Hu C., (2005), User’s Manual. Dep. Ele. Eng. Compu. Sciences. University of California, Berkeley.
21. McCall, (2005), Genetic algorithms for modelling and optimization. J. Comput. Appl. Mathem. 184: 205-222.
22. Suzuki K., Takai N., Sugawara Y., Kato M., (2017), Automatic design of operational amplifier utilizing both equation-based method and genetic algorithm. Trans. 100: 2750-2757.
23. Frank J., Dennard R. H., Nowak E., Solomon P. M., Taur Y., Wong H. S., (2001), Device scaling limits of Si MOSFETs and their application dependencies. IEEE. 89: 259-288.
24. Taur Y., Liang X., Wang W., Lu H., (2004), A continuous, analytic drain-current model for DG MOSFETs. Elec. Dev. Lett. 25: 107-109.
25. Yu F., Huang G., Lin W.,  Xu C., (2018), An analytical drain current model for symmetric double-gate MOSFETs. Adv. 8: 045125: 1-11.
26. Marseguerra M., Zio E., Cipollone M., (2003), Designing optimal degradation tests via multi-objective genetic algorithms. Eng. Sys. Safety. 79: 87-94.
27. Srinivas N., Deb K., (1994), Multi-objective optimization using non-dominated sorting in genetic algorithms. Evolutionary. Comput. 2: 221-248.
28. Deb K., Grawal S. A., Pratap A., Meyarivan T., (2002), A fast and elitist multi-objective genetic algorithm: NSGA-II. Trans. Evolutionary. Comput. 6: 182-197.