Analysis and Design of High Speed 4-2 Compressor in CMOS Technology for High Speed Multipliers

Majlesi Journal of Electrical Engineering

مقاله 14، دوره 12، شماره 4، اسفند 2018، صفحه 105-112   

نوع مقاله: Review Article

نویسندگان

Ali Rahnamaei¹؛ Gholamreza Zare Fatin^{* 2}؛ Abdollah Eskandarian¹

¹Department of Electrical Engineering, Rasht Branch, Islamic Azad University, Rasht, Iran

²University of Mohaghegh Ardabili

چکیده

This review paper contains the discussion about performance analysis of high speed 4-2 compressor architectures, starting from the general idea; conventional form for implementation of this building block along with its truth table has been studied. Thereafter, the modified versions which show promise for high speed multiplier implementations along with their benefits and drawbacks were demonstrated and comprehensively analyzed. Following the same principles, an optimized structure for 4-2 compressor is obtained which has 2 XOR gate level delay for the critical path and contains the least delay among the reported works. As another advantage, because of uniform paths the output waveforms will be free of any glitches. Simulation results for TSMC 0.18 µm CMOS technology and 1.8V power supply using HSPICE have been provided to show the superiority of our designed architecture in terms of the speed performance. Finally, to confirm the correct behavior of proposed compressor, an 8x8 bit multiplier was designed which can operate at the frequency of 500MHz without employing any special multiplication algorithm for partial product generation.

کلیدواژه‌ها

Parallel multiplier؛ Booth Encoder؛ Radix-4؛ High speed

مراجع

[1] P. J. Song and G. D. Micheli, “Circuit and architecture trade-offs for high-speed multiplication,” IEEE Journal of Solid-State Circuits, vol 26, pp. 1184-1198, 1991.

[2] Behrooz Parhami, Computer Arithmetic, Oxford Press, 2000.

[3] M. Rafiquzzaman , Fundamentals of Digital Logic and Microcomputer Design, John Wiley & Sons, 2005.

[4] Andrew D. Booth, “A signed binary multiplication technique,” The Quarterly Journal of Mechanics and Applied Mathematics, Volume IV, Pt. 2, 1951.

[5] A. Karatsuba, and Yu. Ofman, “Multiplication of Many-Digital Numbers by Automatic Computers,” Proceedings of the USSR Academy of Sciences, 145: 293–294, 1962.

[6] C. S. Wallace, “A suggestion for a fast multiplier,” IEEE Trans. on Computers, vol. 13, pp. 14-17, 1964.

[7] L. Dadda, “Some schemes for parallel multipliers,” Alta Frcquetiza, vol. 34, pp. 349-356, 1965.

[8] AC Davies, and YT Fung, “Interfacing a hardware multiplier to a general-purpose microprocessor,” Microprocessors, Volume 1, Issue 7, Pages 425-432, October 1977.

[9] Peiman Aliparast, Ziaadin D. Koozehkanani, and Farhad Nazari, “An Ultra High Speed Digital 4-2 Compressor in 65-nm CMOS,” International Journal of Computer Theory and Engineering, Vol. 5, No. 4, August 2013.

[10] Ohkubo N., Suzuki M., Shinbo T. et al., “A 4.4 ns CMOS 54 54-b Multiplier Using Pass-Transistor Multiplexer,” IEEE Journal of Solid-State Circuits, Vol. 30, Issue 3, pp. 251-257, 1995.

[11] Wen-Chang Yeh and Chein-Wei Jen, “High-Speed Booth Encoded Parallel Multiplier Design,” IEEE Transactions on Computers, Vol. 49, No. 7, July 2000.

[12] Hsin-Lei Lin, Chang R.C. and Ming-Tsai Chan, “Design of a Novel Radix-4 Booth Multiplier,” The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, Vol. 2, pp. 837-840, 2004.

[13] Shiann-Rong Kuang, Jiun-Ping Wang, and Cang-Yuan Guo, “Modified Booth Multipliers With a Regular Partial Product Array,” IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 56, No. 5, pp. 404-408, May 2009.

[14] A. Fathi, S. Azizian, R. Fathi, H.G. Tamar, “Low latency, glitch-free booth encoder-decoder for high speed multipliers,” IEICE Electronics Express, Vol. 9, No. 16, pp. 1335-1341, 2012.

[15] A. Fathi, S. Azizian, Kh. Hadidi, A. Khoei, “Ultra High Speed Modified Booth Encoding Architecture for High Speed Parallel Accumulations,” IEICE transactions on electronics, Vol. 95, No. 4, pp. 706-709, 2012.

[16] Honglan Jiang, Jie Han, Fei Qiao, and Fabrizio Lombardi, “Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation,” IEEE Transactions on Computers, Vol. 65, No. 8, pp. 2638-2644, Aug 2016.

[17] Liu, Weiqiang, et al, “Design of approximate radix-4 Booth multipliers for error-tolerant computing,” IEEE Transactions on Computers (2017).

[18] Oklobdzija V.G., Villeger D., and Liu S.S., “A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach,” IEEE Transactions on Computers, Vol. 45, no. 3, pp. 294-306, Mar. 1996.

[19] D. Radhakrishnan and A. P. Preethy, “Low-power CMOS pass logic 4-2 compressor for high-speed multiplication,” in Proc. 43rd IEEE Midwest Symp. Circuits Syst., vol. 3, 2000, pp. 1296–1298.

[20] Chip-Hong Chang, Jiangmin Gu, and Mingyan Zhang, “Ultra Low-Voltage Low-Power CMOS 4-2 and 5-2 Compressors for Fast Arithmetic Circuits,” IEEE Transactions on Circuits and Systems I, Vol. 51, Issue 10, pp. 1985-1997, 2004.

[21] Amir Fathi, Sarkis Azizian, Khayrollah Hadidi and Abdollah Khoei, “A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations,” IEICE Trans. Electron., Vol. E95-C, No. 4, April 2012.

[22] Amir Fathi, Sarkis Azizian, Khayrollah Hadidi, Abdollah Khoei and Amin Chegeni, “CMOS Implementation of a Fast 4-2 Compressor for Parallel Accumulations,” 2012 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1476-1479, May 2012.

[23] A. Momeni, J. Han, P.Montuschi, and F. Lombardi, “Design and Analysis of Approximate Compressors for Multiplication,” IEEE Transactions on Computers, Vol. 64, No. 4, pp. 984-994, 2015.

[24] Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram, “Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 4, pp. 1352-1361, 2017.

[25] Minho Ha, and Sunggu Lee, “Multipliers with Approximate 4-2 Compressors and Error Recovery Modules,” IEEE Embedded Systems Letters, Volume: PP, Issue: 99, Aug 2017.

[26] A. Weinberger, “4:2 Carry-Save Adder Module,” IBM Technical Disclosure Bull., Vol. 23, Jan. 1981.

[27] Dinesh Kumar, and Manoj Kumar, “Modified 4-2 compressor using improved multiplexer for low power applications,” IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2016.